The present invention relates to the fabrication of a low capacitance transistor cell element particularly adaptable for use in both large and very large scale integrated circuits. By being constructed to have a lower capacitance for effective transistor size, the present invention permits fabrication of higher density array devices that are both faster and more efficient than existing integrated circuits. The size of the transistor element according to the present invention allows the chip fabricator to reduce the size of an integrated circuit chip whereby the dice yield realized from standard wafer fabrication techniques is greatly enhanced, and the costs of such integrated circuits are correspondingly reduced.
In the last 20 years, improvements in fabrication technology have permitted integrated circuits to become so dense that a single chip may contain hundreds of thousands of transistor cell elements. Indeed, very large scale integrated systems containing millions of transistor elements, are anticipated with these transistor elements acting as switches with which digital systems may be designed. The present invention is directed toward a transistor cell element that can be utilized in an array for such large scale integrated systems as a step toward further densifying the electronic circuitry in such devices.
The basic properties of a metal-oxide-semiconductor (MOS), field-effect transistor (FET) have been understood for some time, and the fabrication of MOSFET transistor cell elements has been known and employed in the design of large scale integrated circuits. Typically, integrated systems and MOS technology contain three levels of conducting material separated by intervening layers of insulating material. The actual transistor cell is formed of diffusion regions which are crossed by paths of polysilicon so that a channel region is defined underneath the polysilicon, and the polysilicon is separated from the channel by a relatively thin layer of oxide material. The polysilicon path, otherwise known as the gate, acts as a switch for the electrical part between a pair of separated diffusion regions. One side of the diffusion region is known as the source, and the other side of the diffusion region is commonly known as the drain. In the absence of a biasing voltage on the gate, no current flows between the source and the drain; however, when a switching voltage is placed on the polysilicon gate, charge carriers are drawn into the channel region so that an electrical route is provided between the source and the drain. The polysilicon gate is separated from the substrate by a layer of thin oxide, as noted above, which forms a capacitor that is an inherent part of the transistor element. Additional capacitance factors are inherent in MOSFET design, predominantly as a result of depletion regions and diffusion edge effects. The total capacitance of this transistor cell element greatly affects the response time of the system of transistor cell elements since several transistors must be interconnected to produce a logic circuit.
Traditional fabrication techniques for transistor cell elements generate rectangularly-shaped transistor elements wherein facing rectangular regions contain diffused dopant which are separated by a linear channel region and are bounded by isolation regions extending therearound. The resistance of such a transistor cell element decreases with an increase in its width, as defined by the length of the channel, but the capacitance of the element increases as the width increases. While the gate to channel capacitance is normally the largest capacitance for a given transistor cell element, another significant capacitance occurs where a diffusion layer, for example an n-type diffusion forming the drain, is positively biased with respect to the bulk silicon and the isolation region. The positive biasing on the n-type region causes a depletion layer to be formed beneath the diffusion. Accordingly, a capacitance region is formed that is proportional to the area of the drain and inversely proportional to the thickness of the depletion layer. Since the isolation region for this type of device is normally highly doped p-type material that receives the voltage bias of the well in which it is formed, with the well usually being held at ground potential, there is a substantial capacitance between the sidewall of the isolation region and the drain. It is desireable to minimize the total capacitance of the transistor element, where possible.
While prior art devices comprising the linear transistor cell elements have proved quite functional in fabrication and operation, there remains a need for a lower capacitance transistor cell element configuration which can reduce the costs and improve the performance of large scale integrated devices. The development of the transistor cell element having a large effective transistor width while having a lower capacitance is needed for use in an array where such can be produced by existing fabrication technology.